Section 15.4 of the i960RP Microprocessor User's Manual has a good description of PCI Configuration cycles as understood by the bridge unit.
The devices on the secondary PCI bus can be marked private or public by setting the appropriate bit in the Secondary IDSEL Select Register (SISR) of the i960RP bridge unit.
Table 
lists all the devices, and the corresponding bit in
the SISR register. For each device, if the bit is set the device is
made private. Device ID 5 (Daughter card #4) is public, and nothing
can be done about that. If the DEC bridge is made private, then all
the devices downstream from it are also private.
Making a device private works by suppressing TYPE-1 to TYPE-0 conversions when the SISR bit for the device is set. It is important that the SISR register not be changed after the host BIOS has been granted access to the i960RP bridge. If the private bit for a device is turned on after the BIOS configures the device, the host will still believe that the device is there and will still be able to access it. Only the configuration space will become inaccessible.
If the DEC bridge is made private, then all the devices behind it are also private. On the other hand, If the DEC bridge is public, the IMC image and any CIP design must be loaded before configuration cycles are enabled. The host BIOS will probe the bridge and devices behind it and will set the bridging window (which is direct mapped) no smaller then the size needed to access the devices it finds behind the bridge. If the CIP or IMC images are loaded after BIOS initialization, the configured window will not be large enough to add in the new memory regions.
