ISE: Imaging Subsystem Engine

Technical Description
Picture Elements, Inc.
303 444-6767

Copyright 1996, Picture Elements Inc.


The Picture Elements Imaging Subsystem Engine (ISE) is the first of a new breed of imaging boards. With its strong emphasis on grayscale manipulation, a new realm of image quality is achievable in document imaging, especially for those applications where binary images are the end result. Functioning as more than a simple scanner interface board, the ISE board forms the core of an entire input subsystem capable of producing the highest in image quality directly from the raw grayscale of the leading scanner engines.

General Description

The Imaging Subsystem Engine (ISE) is a PCI bus board that is optimized for performing data intensive image processing functions. It performs these tasks using a combination of on-board software, programmable hardware, and dedicated hardware. The goal is to achieve state-of-the-art performance at a reasonable cost, using newly emerging standards wherever possible.

A main board/daughter board architecture is used for flexibility and to permit the updating of features in the short development times for which Picture Elements is widely renowned.

Main Board

The main ISE board is intended to provide all of the general purpose resources that are needed for data intensive image processing, along with expansion connectors for application specific processing daughter boards (up to 7), memory expansion (up to 64 MBytes total), and peripheral support.

Main Board Bus

The primary PCI bus (from the host computer) connects through the edge connector to an Intel 960RP processor, which also operates as a bridge to the secondary PCI bus. This secondary PCI bus is the main internal bus of the ISE board. The 960RP processor also has a local bus which has 4 MBytes of processor DRAM memory and a 512 KByte "boot" flash memory, allowing the processor to execute its software at full speed without consuming the bandwidth of either PCI bus.

Programmable Grayscale Image Processing

A programmable image processor (a field programmable gate array with 128 KBytes of SRAM) is also included on the main ISE board. This can be dynamically configured to perform a variety of image processing functions. The initial release of the board includes the functions grayscale deskew and grayscale domain image scaling. Planned functions include scale to gray, contrast stretching and connected component analysis. These functions are well suited to hardware implementation, but VLSI chips are not commercially available for most of them. Programmable hardware is the most economical solution.

Memory: Variable Size, High-Speed

The main image memory on the ISE board uses synchronous DRAM (SDRAM), which currently offers the best price/performance for large, high bandwidth random access memory.

The standard ISE configuration has 16 MBytes of on-board SDRAM memory, but configurations from 8 MBytes to 32 MBytes are available. Adding a mezzanine board allows expansion up to 64 MBytes.

The SDRAM data bus operates at 200 MBytes/second and is connected to both the programmable image processor and to the 133 MByte/second secondary PCI bus via rate buffer FIFOs, allowing multiple, high-bandwidth operations to be performed simultaneously with minimal interference to each other.

Powerful Daughter Boards

There are four slots available for expansion daughter boards on the top (component) side of the ISE board, and optionally three more on the bottom side. Each application specific daughter board is of a size generous enough to allow several VLSI components and associated memory chips to be used for each function.

A number of daughter boards are planned for the most essential functions in document image processing. Custom development of special-purpose accelerators is also planned. These developments will leverage off Picture Elements’ strength in conceiving and delivering imaging algorithms at the highest scanning speeds.

DMST Daughterboard: Multi-Scale Thresholder

The DMST Daughter Board uses two Picture Elements VST-1000 integrated circuits to perform the highest quality binary thresholding and despeckling. Multiple thresholded versions may be produced from the same source grayscale image. The source grayscale image may be grayscale deskewed and grayscale scaled to any resolution (including higher than native optical resolutions) prior to the thresholding operation.

DBIN Daughterboard: Group 4 and JBIG Compressor / Decompressor

The DT6 Daughter Board compresses binary data produced by the DMST Daughter Board or received from a scanner using the international standard ITU-T Recommendation T.6 compression algorithm (often called CCITT Group 4) or the JBIG compression technique (Recommendation T.82).

DJPG Daughterboard: JPEG Compressor / Decompressor

The DJPG Daughter Board compresses grayscale data according to the international standard baseline JPEG algorithm (ISO 10918-1 and ITU-T Recommendation T.81). The source grayscale image may be grayscale deskewed and grayscale scaled to any resolution prior to this compression process.

Flexible Input / Output Ports

General purpose I/O expansion is provided via one interface daughterboard with access to the ISE board’s rear panel, which is user-accessible. Planned I/O boards include custom-developed video-style scanner interfaces (e.g. the Fujitsu-type interface).

DFUJ Daughterboard: Fujitsu-Style Video Interface

This interface accepts differential or single-ended data from scanners compatible with the Fujitsu-style video interface and provides a UART for scanner control.

DMIN Daughterboard: Minolta Grayscale Interface

This interface accepts grayscale data from a Minolta PS 3000 face-up book scanner. A brightness tracking circuit finds the significant brightest values on the page for use by the contrast stretching circuitry on the main board.

Last modified: 11 November 1996

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Copyright 1996-1997 Picture Elements, Inc.