The ISE board is designed to reset with the i960RP in the configuration cycle retry mode. In this mode, the i960RP PCI interface, including the PCI-to-PCI bridge and therefore the entire board, will retry all PCI configuration cycles until specific action is taken. The i960 core, in the mean time, is free to bootstrap as soon as the RST# is de-asserted.
The i960 reads from the flash memory an initial boot record (IBR) that includes some minimal configuration for the flash itself, and a start address for the reset code. Once the i960 is running, the bootstrap software configures the hardware on the board as necessary to make it presentable to the host. This includes configuring the memory, moving program code into DRAM and loading CIP and IMC configurations. The i960 does not access any PCI configuration registers or PCI register sets of any devices on the board. It just makes the board PCI compatible.
Once this reset initialization is done, the i960 turns on the PCI bus by turning off the configuration cycle disable bit. This allows the host BIOS access to the PCI busses throughout the ISE board, and all the address space arrangements are made by the host computer. The i960 does not need to participate in any of this.
When the BIOS is done arranging the address space, the operating system on the host computer is loaded. Eventually, a device driver for the ISE board (normally application specific, due to the nature and intended use of the ISE design) contacts the i960 and any other devices on the board as needed.
All the PCI devices, including daughter cards, are accessible to the
host through the various bridges,
although the host software will typically not bother with the other
devices and will mainly communicate with software running on the i960
processor. However, there will be times when the host needs to access
various ISE devices, or daughter cards need access to the host
memory. The bridges make such accesses possible, assuming the host
BIOS configurator creates the image of a large, mutually consistent
bus address space.
That is the theory and the intent, but there are cases where reset behavior needs to be slightly different. For example, testing and debugging the i960 software may require that the host have access to the board even when the i960 is held reset, or perhaps for manufacturability the bootstrap software must be written to the flash memory through the primary PCI interface. For this and other purposes, the reset mode can be controlled by jumpers.