The CIP is a field programmable gate array. Designing programs for this device requires design and synthesis tools suitable for generating configuration images for Xilinx XC4000 FPGAs, so is not generally considered a software task. Also, the registers available to software in the CIP depends on the design loaded into it.
The CIP has pins connected to the local PCI bus and the high speed memory bus so can be used to manipulate images in the fast DRAM and can communicate with other daughter cards or the i960 processor (or the host computer directly, given appropriate configurations elsewhere).