Use this proceedure to load the Image Memory Controller, as well.
Once the hardware designer has designed the function of the FPGA and synthesized a configuration image suitable for loading into the CIP, use the following procedure to load the image. In the following pseudo-code, CDIN and CCLK are the appropriate signals from the ISE_CONTROL register.
CDIN <= 1;
CCLK <= 1;
for each byte in the image begin
-- Each iteration takes 90ns
for bit in 7 downto 0 loop
CDIN <= byte(bit);
CCLK <= 0 after 45ns, 1 after 45ns;
end loop;
end;
The high bit of each byte is written first, down to the low bit of the byte last. The i960rp is clocked at 33MHz, so the CPU clock lasts 30ns even without external bus cycles and wait states. Therefore, the timing constraints should be very easy to meet. Just remember that the CDIN bit is stored on the rising edge of CCLK.
The control bits used in this procedure all exist in the ISE_CONTROL register. When not programming one of the FPGAs, leave the unused CDIN and CCLK bits zero.
When the FPGA device configuration has been loaded, the corresponding CDONE bit in the ISE_STATUS register is turned on(1). This bit then remains on until the board is reset. The CDONE bit can alse be tested to determine if the device has already been loaded.
See the section ISE Miscellaneous Devices for details of the location and bit arrangement of these registers. The i960RP must be configured to access these registers before the FPGA devices can be configured.