This is a Field Programmable Gate Array (FPGA) connected to both the
local PCI bus and the high-speed memory bus. It is configured by
software to contain designs that manipulate data at high speeds. The
configuration images are Xilinx designs prepared by Picture
Elements, Inc. Examples of planned functions are gray-scale image
scalers, 
rotators, and binary video connected component
analysis.
The CIP has access to both the Tertiary PCI bus and the high speed memory bus. The local memory bus gives the CIP access to high speed synchronous DRAM and so allows for the fast execution of image manipulation algorithms. The connection to the Tertiary PCI bus allows it access to several daughter cards, and the i960RP (through the DEC bridge) and host memory through both bridges.