The i960RP has connected to it 4 MBytes of DRAM, arranged as one leaf of EDO DRAM. Because of the design of ram chips and their attachment, there are few choices to be made. Configure the DRAM registers as
in Table 
. See the i960RP Microprocessor User's Manual,
Section 14.5-DRAM Control.
The setting of the DBAR register places the DRAM at 0xA0000000 in the address space. There are many reasonable places in the address space to place the DRAM, each as good as the next, but software shipped by Picture Elements sets up the DRAM at this location. This address avoids the various i960 reserved regions, the direct map region and the outbound translation windows. See Table 12-1. PMCON Address Mapping in the i960RP User's Manual.
The PMCON for the DRAM must set bus width to 32 bits for proper operation of the DRAM.
