There are two registers connected to the i960RP local bus and CE1#. One, ISE_STATUS, is read-only and 10 bits wide. The other, ISE_CONTROL, is write-only and 8 bits wide. Both are fast enough to not require any wait states, and can be accessed by 32 bit bus arrangement. See the i960RP Microprocessor User's Manual, section 14.4: Memory Bank Programming Registers.
Table 4: Memory Configuration for Misc. Registers
These settings place the registers at 0xB0000000, which shares the PMCON10_11 region with DRAM. That is fine as both require 32 bit bus width setting.
The ISE_CONTROL register has the following pertinent bits. The others are reserved and should be written as zeros. These bits are write-only.
Table 5: ISE_CONTROL Register Bits
The xxx_CDIN and xxx_CCLK bits are signals to the memory bus DMA controller chip and the CIP device, used only for loading device configurations.
The ISE_STATUS register
Table 6: ISE_STATUS Register bits
is described in Table 
. The active low
ISE_PRSNTx# bits are connected to the respective daughter
cards on the ISE board. The bit is zero(0) for each board that is
present, one(1) otherwise.
The xxx_CDONE bits are signals from the DMA controller chip and the CIP device, used during download of device configuration. These bits will be used at reset to check that the chip configuration has been loaded into the respective programmable part.