The interrupt controller for the i960JF core has many complex features, but the i960RP interrupts are direct mapped, so much of the complexity goes away. The ISE board connects certain devices to various external interrupt pins, so they need to be mapped.
The ISE board also has an external non-maskable interrupt signal, connected to a debounced pushbutton. This is only available after the Image Memory Controller has been configured, as that device arranges for the debouncing of the pushbutton.
The DMA controller for the high speed memory bus uses this signal to interrupt the i960.
Daughter cards number 1 and 2 share this interrupt. The INTA# signals from the two cards connect here.
Daughter cards number 3 and 4 share this interrupt. The INTA# signals from the two cards connect here.
Daughter card number 5 has this interrupt signal alone. The INTA# signal from the card connects here.
Daughter cards number 6 and 7 share this interrupt. The INTA# signals from the two cards connect here.
The Configurable Image Processor chip is connected to this interrupt.
Only internal i960RP devices use this interrupt.
Only internal i960RP devices use this interrupt.
The i960RP XINT0 - XINT3 may be configured to route these interrupt signals to the P_INTx# pins. However, on the ISE board only the P_INTA# signal is connected so routing to these pins is not meaningful and should not be done. Therefore, the PIRSR register must be set to 0.
Other registers for configuring the i960 interrupt controller map the interrupts to priority numbers and enable or disable them. Nothing about the ISE board places special requirements on the settings, but Picture Elements software sets them to the following values:
The ICON.gie bit is implicitly manipulated by the inten and intdis instructions. For a complete description of the i960RP interrupt controller, see Chapter 8 of the i960RP Microprocessor User's Reference Manual.